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SlateBlue



Joined: 23 Aug 2015
Posts: 75

PostPosted: Sat Apr 15, 2017 6:08 pm    Post subject: Reply with quote

I've created a spreadsheet and have documented what I've toned out so far. The way I have it laid out makes sense to me, although I have not tried to discern any kind of pattern. It would appear to me, through visual inspection, that some of the pins on each memory chip are connected in parallel. Does this make sense?

[url=https://docs.google.com/spreadsheets/d/1IEQZNNyqNDBm2rji7DHeYrpfK_TktUw3WzUsdI8wsJM/edit?usp=sharing]
Link To Spreadsheet[/url]

I'm going to take a break and go watch Lifetime movies with my wife. Wink
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bobo68



Joined: 03 Jun 2015
Posts: 194
Location: Germany

PostPosted: Sun Apr 16, 2017 3:22 am    Post subject: Reply with quote

I'll have a look at the spreadsheet. Of course that makes sense, (most of) the address lines would be connected to all address inputs of the RAM chips. Same for read/write signal lines.
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bobo68



Joined: 03 Jun 2015
Posts: 194
Location: Germany

PostPosted: Sun Apr 16, 2017 6:17 am    Post subject: Reply with quote

SlateBlue wrote:
This board has many vias, those vias appear to connect to some internal traces and I can't see where they go. It would appear to me that the ground plane exists on the side opposite of where the components are mounted. So, I then assume the Vcc plane exists on the component side. Thus, ground pins would be on the backside of the module, and Vcc pins would be on the front. Is this correct?


Most probably not. I do not know if there is really one ground and additionally one Vcc layer (plane). It could just be a ground layer and direct connections (via distinct traces) for Vcc.

A via can go to any other layer, either an internal one or through to the other outer layer.

I do not know what you mean with the ground pins on the backside etc. The pins of the SIMM module do not have two separate sides, they are connected.

In your spreadsheet we will need to document inter-component connections, too.
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bobo68



Joined: 03 Jun 2015
Posts: 194
Location: Germany

PostPosted: Sun Apr 16, 2017 6:44 am    Post subject: Reply with quote

Here is the DSP expansion slot as documented in the 33MHz NeXT Color Slab Motherboard Schematics: http://www.nextcomputers.org/NeXTfiles/Docs/Hardware/Schematics/Turbo_slab/CSlab33-09.pdf

It says that pin 42 of the SIMM is _DSPDS which is (inverted) data select. Interesting to see that the guys who build the large DSP memory module did not use the pin but inverted _DSPPS to get _DSPDS. From the 56001 documentation these seem to be mutually exclusive (either program memory or data memory and data memory could be x memory or y memory signaled by DSPXY).

There is some other interesting information here https://heller.userweb.mwn.de/NeXT/HW_internal_FAQ.txt

Code:
Subject: L10. How to expand DSP memory?

The Speech Recognition Lab at San Francisco State University has
developed a DSP memory expansion board for the NeXT computer that
provides the maximum memory supported by the DSP56001 processor.

...

Note: Because we've organized our memory as three separate
(non-overlapping) banks (X, Y and P) of 192KB apiece, none of the DSP
memory image functionality provided by NeXT with its existing 8K base
configuration, or its 96KB DSP expansion module is supported. While we
cannot guarantee that every existing DSP application ever written will
be plug-and-play compatable with our DSP expansion memory, we are not
aware of any existing applications that use the image functionality.
The MusicKit, and demo programs that use the DSP, such as Mandlebrot
and ScorePlayer, work fine with our memory module.


Sounds like NeXT used some kind of memory overlay scheme ("image"?) to me. We will find out when we understand the wiring of the multiplexer.
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SlateBlue



Joined: 23 Aug 2015
Posts: 75

PostPosted: Sun Apr 16, 2017 9:04 am    Post subject: Reply with quote

bobo68 wrote:
SlateBlue wrote:
This board has many vias, those vias appear to connect to some internal traces and I can't see where they go. It would appear to me that the ground plane exists on the side opposite of where the components are mounted. So, I then assume the Vcc plane exists on the component side. Thus, ground pins would be on the backside of the module, and Vcc pins would be on the front. Is this correct?


Most probably not. I do not know if there is really one ground and additionally one Vcc layer (plane). It could just be a ground layer and direct connections (via distinct traces) for Vcc.

A via can go to any other layer, either an internal one or through to the other outer layer.

I do not know what you mean with the ground pins on the backside etc. The pins of the SIMM module do not have two separate sides, they are connected.

In your spreadsheet we will need to document inter-component connections, too.

Yes, disregard. I forgot this was a SIMM when I made that comment.
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SlateBlue



Joined: 23 Aug 2015
Posts: 75

PostPosted: Sun Apr 16, 2017 9:29 am    Post subject: Reply with quote

bobo68 wrote:
In your spreadsheet we will need to document inter-component connections, too.

Agreed. I figured I would start by figuring out where each pin on the SIMM connects to. I am going now to have Easter lunch with some friends and will return this afternoon.
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bobo68



Joined: 03 Jun 2015
Posts: 194
Location: Germany

PostPosted: Sun Apr 16, 2017 12:10 pm    Post subject: Reply with quote

bobo68 wrote:
Sounds like NeXT used some kind of memory overlay scheme ("image"?) to me. We will find out when we understand the wiring of the multiplexer.


According to the DSP56001 24-BIT DIGITAL SIGNAL PROCESSOR USERíS MANUAL an overlay scheme should not be present:

Code:
The program memory select, data memory select, and X/Y select can be considered additional address signals, which extend the addressable memory from 64K words to 192K words


But who knows what NeXT made out of it.
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SlateBlue



Joined: 23 Aug 2015
Posts: 75

PostPosted: Sun Apr 16, 2017 1:31 pm    Post subject: Reply with quote

bobo68 wrote:
Here is the DSP expansion slot as documented in the 33MHz NeXT Color Slab Motherboard Schematics: http://www.nextcomputers.org/NeXTfiles/Docs/Hardware/Schematics/Turbo_slab/CSlab33-09.pdf

It says that pin 42 of the SIMM is _DSPDS which is (inverted) data select. Interesting to see that the guys who build the large DSP memory module did not use the pin but inverted _DSPPS to get _DSPDS. From the 56001 documentation these seem to be mutually exclusive (either program memory or data memory and data memory could be x memory or y memory signaled by DSPXY).

There is some other interesting information here https://heller.userweb.mwn.de/NeXT/HW_internal_FAQ.txt

Code:
Subject: L10. How to expand DSP memory?

The Speech Recognition Lab at San Francisco State University has
developed a DSP memory expansion board for the NeXT computer that
provides the maximum memory supported by the DSP56001 processor.

...

Note: Because we've organized our memory as three separate
(non-overlapping) banks (X, Y and P) of 192KB apiece, none of the DSP
memory image functionality provided by NeXT with its existing 8K base
configuration, or its 96KB DSP expansion module is supported. While we
cannot guarantee that every existing DSP application ever written will
be plug-and-play compatable with our DSP expansion memory, we are not
aware of any existing applications that use the image functionality.
The MusicKit, and demo programs that use the DSP, such as Mandlebrot
and ScorePlayer, work fine with our memory module.


Sounds like NeXT used some kind of memory overlay scheme ("image"?) to me. We will find out when we understand the wiring of the multiplexer.

What is meant by memory overlay? Does this refer to how the memory is managed?
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bobo68



Joined: 03 Jun 2015
Posts: 194
Location: Germany

PostPosted: Mon Apr 17, 2017 3:24 am    Post subject: Reply with quote

Overlay means in this case that the logical memory space (as addressed by the bus) is mapped to the physical memory (as provided by the SRAMs) in such a manner that more than one logical address spaces is mapped to the same physical address space.

I introduced an address mapping table in the Google sheet which shows my current understanding.

It is done by the multiplexer, which uses the DSPA15 bus signal to either provide bus DSPA14 or bus DSPXY line (inverted) to A14 of the SRAM. By that the 192 K word address space (64 K of program, data x and data y memory) is mapped to 32 K SRAM address space in some weird manner.
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SlateBlue



Joined: 23 Aug 2015
Posts: 75

PostPosted: Mon Apr 17, 2017 8:12 am    Post subject: Reply with quote

I have added comments where original notes were ambiguous. It appears _DSPDS is still in question, so I will work to see if there is any correlation with pin 42 of the SIMM.
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