50MHz Turbo Color Slab

[gborgns]

5/25/09 - Added corrected schematic and a couple of pictures showing a completed working system with homemade doubler.
10/22/11 - Edit post to reflect new local file location.
4/7/2023 - Added images to post - Admin

As promised I am documenting what I did to run my NeXT Turbo Color Slab at 50 MHz (also a NeXT Color Slab).

Below is a link to a marked up schematic of a TurboC mainboard, showing where the clock doubler needs to be inserted to make this work.  Added a correction to U6 to force board to think it is running at 33MHz, regardless of speed switch setting.  I found if I didn't do this, the motherboard thought it was running at 25MHz when set to 50MHz. This caused VRAM errors on boot.

Link: Marked up Turbo Color Schematic

Link: Processor and connections
Shows where connections are made to the mainboard and the installed processor. Note PC type heat sinks on key IC's.


Link: Doubler and power connection
Power connections to the quaddoubler and mainboard. Note PAL removed from quaddoubler to conserve on power.


Link: Closeup of power tap
Connected to mainboard +5VDC across capacitor.


Link: Processor and doubler
Shows power connections to quaddoubler.


Link: Completed installation
Completed installation showing speed select switch and second internal hard drive.


Link: Close up of connections to/from Turbo Mainboard
Connect jumper JP11 pads to change system clock to 50MHz. Ground connection used for shield grounds (I found that the SMD test points were a pain to solder to, they lift at the slightest touch of heat. Solder directly to the board instead).


Link: Homemade clock doubler
Doubler based on Quaddoubler with the exact circuitry listed in the Motorola spec. sheet on the MC88916. I used a SIP prototype PCB with a copper tape ground plane added on the bottom. Works as advertised.  Note that the IC is upside down in the picture.


Link: Schematic for homemade clock doubler
Schematic for the homemade clock doubler.  All capacitors are ceramic and resistors thick film.


Link: Ready for doubler
Close-up of the NeXT mainboard prepped and ready for the doubler.


Note the MC88915 is now a 100 Megahertz version verses the stock 70 Megahertz part.

The jumper is used to select the speed and the extra 1100 ohm resistor is used to pull the speed select line down to ground, since the board was actually a 25 MHz Color board to start with.

Link: Full View before doubler
The full board before the doubler circuit is added.


Note the fan and the now socketed processor. I removed the original processor, which was directly soldered into the board, and replaced it with socket (removal required a solder-pot and a vacuum solder removal tool). The new processor is a 40 MHz version with an aggressive cooling solution (a large heat sink and fan) taken from a Newertech 50 MHz Mac upgrade card.

Link: Doubler Installed
The full board, doubler installed.  Note jumper on U6 just above and right of the processor.


Link: Completed installation
Completed installation, ready for cover.

[Slab]

I noticed that you used a 25Mhz Turbo as a platform for this cool mod.  Would this procedure work with the more common 33Mhz Turbo?  Thanks for posting the pictures and detailed info.

[gborgns]

Yes, in fact my original prototype 50 MHz mod used a 33 MHz Turbo Color slab.  

I used a 25 MHz Color slab for this mod because, it has the same chip set as a Turbo Color Slab (it is essentially a 33 MHz system wired for 25 MHz), I didn't want to mess with my working 50 MHz turbo slab, and I got the Color slab cheap on ebay.

I also wanted to try the mod on another system, just to make sure the prototype system wasn't just a fortunate fluke.

[da9000]

This is a very cool hack!

But I have a couple of questions for the knowledgable hardware hackers:

1) Am I correct in understanding that for the first set of photos you used the Sonnet Quaddoubler but not the entire piece, but only the clock doubling part of it, in order to double the speed?

2) Does the doubled clock go straight into the CPU, or does it also double the BUS/peripheral chip clocks? I think it's the first, because a 50Mhz bus would blow up :-)

3) I'm not certain why you wouldn't place the Sonnet Quaddoubler in the motherboard CPU socket, and the CPU in the Sonnet Quaddoubler CPU socket. Is the reason that it physically won't fit in the case?

4) Assuming that it physically fitted in the case without a problem, would the Sonnet Quaddoubler work right-off the bat (as described in question 3: place CPU in Sonnet's CPU socket, place Sonnet in motherboard CPU socket) ? Or would there still be need for motherboard modifications? My guess is that it would work right away, unless one wanted to have a switch between slow/fast (like your JP11)

5) I understand why the PAL was removed, but I'm curious: do you know what its purpose or use was?

6) You said the MC88915 is now a 100Mhz piece as opposed to 70Mhz. Does that imply that it can double a maximum of 50Mhz clock to a maximum of 100Mhz clock? So therefore the maximum overclock for a NeXT would be 100Mhz (with this chip)

7) Could you please list the values of the SMD caps and resistors for the homemade quaddoubler?

Where did you buy the MC88915 chip, or should it be an MC88916 (the latter is in the photos)?

Thanks!

[helf]

wow, that actually looks fairly easy to do.

*grabs soldering gun*

[gborgns]

da9000

I'll try answer your questions.  It's been a while since I did the mod and a lot of projects have past by me since.

Q1) Am I correct in understanding that for the first set of photos you used the Sonnet Quaddoubler but not the entire piece, but only the clock doubling part of it, in order to double the speed?

A1) Yes, I used the clock doubler circuit and the 040 cooling solution from the Sonnet Quaddoubler.

Q2) Does the doubled clock go straight into the CPU, or does it also double the BUS/peripheral chip clocks? I think it's the first, because a 50Mhz bus would blow up.

A2) Almost the entire processing portion of the computer is accelerated to a base clock of 50MHz, including the memory and SCSI interfaces.  This requires the use of faster memory and more modern SCSI drives.  We are only accelerating from 33MHz to 50MHz, so it really isn't that much of a stretch.

Q3) I'm not certain why you wouldn't place the Sonnet Quaddoubler in the motherboard CPU socket, and the CPU in the Sonnet Quaddoubler CPU socket. Is the reason that it physically won't fit in the case?

A3) The Quaddoulber I had was socket keyed such that it would not plug into the processor socket without interference with the case.

Q4) Assuming that it physically fitted in the case without a problem, would the Sonnet Quaddoubler work right-off the bat (as described in question 3: place CPU in Sonnet's CPU socket, place Sonnet in motherboard CPU socket) ? Or would there still be need for motherboard modifications? My guess is that it would work right away, unless one wanted to have a switch between slow/fast (like your JP11)

A4) No, the stock Quaddoubler works only with an 040 MAC and used a PAL to sense when a bus relinquish signal was active.  The PAL allowed a doubled clock signal to clock the processor during the bus relinquish periods.  This allowed the processor to run at a faster rate than the system bus.  This signal is not used in the NeXT computer.  The bus is never released.  The entire computer must be synchronized to the new clock frequencies.  The NeXT is a very different animal than the MAC.

Q5) I understand why the PAL was removed, but I'm curious: do you know what its purpose or use was?

A5) See A4)

Q6) You said the MC88915 is now a 100Mhz piece as opposed to 70Mhz. Does that imply that it can double a maximum of 50Mhz clock to a maximum of 100Mhz clock? So therefore the maximum overclock for a NeXT would be 100Mhz (with this chip).

A6)  The 040 requires two clocks, one at twice the base clock frequency.  So a 33MHz 040 also has a 66MHz clock applied to it which is provided by the 70MHz rated MC88915.  So yes, the maximum clock out of the new MC88915 is 100MHz (it actually has a higher frequency signal available, but it is not used), but that is what a 50MHz 040 requires, 50MHz and 100MHz.

Q7) Could you please list the values of the SMD caps and resistors for the homemade quaddoubler?

A7)  The values are right out of the MC88916 data sheet, page 8:   MC88916    Now manufactured by idt.  
I used 1206 sized passive parts, to make it easier to hand assemble.  I bought all the parts for the doubler circuit from Digi-Key, including the MC88915 and MC88916 parts.  Remember to use a ground plane circuit board and plenty of bypass capacitors, since there will be high frequencies running around on the board.

Since idt has taken over production of the MC series of parts you may have to search a bit to find a new retail source for the MC88915 and MC88916 parts (Digi-Key still had a few Freescale parts in stock).

I hope someone else will try this mod and take it even further.

[da9000]

Hi gborgns. Thanks for the detail answers! A couple more questions from me...

Almost the entire processing portion of the computer is accelerated to a base clock of 50MHz, including the memory and SCSI interfaces.  This requires the use of faster memory and more modern SCSI drives.

Q8 ) When you say faster memory, do you mean < 70ns? Or did 70ns work well?

No, the stock Quaddoubler works only with an 040 Mac and used a PAL to sense when a bus relinquish signal was active.  The PAL allowed a doubled clock signal to clock the processor during the bus relinquish periods.  This allowed the processor to run at a faster rate than the system bus.  This signal is not used in the NeXT computer.  The bus is never released.  The entire computer must be synchronized to the new clock frequencies.  The NeXT is a very different animal than the MAC.

Aha. That's very interesting.

Q9) Does the above imply that the 040 on a Mac was alternating between the doubled clock and the non-doubled clock as per bus utilization? In other words, a cure/primitive "power saving" mode based on crude "frequency scaling" ?

The 040 requires two clocks, one at twice the base clock frequency.  So a 33MHz 040 also has a 66MHz clock applied to it which is provided by the 70MHz rated MC88915.  So yes, the maximum clock out of the new MC88915 is 100MHz (it actually has a higher frequency signal available, but it is not used), but that is what a 50MHz 040 requires, 50MHz and 100MHz.

I'm a little confused. In your photos I see the MC88916 (@ 70Mhz and @ 80Mhz) being used, instead of the MC88915 @ 100Mhz.

Q10) How were these able to provide a 100Mhz clock? If the input frequency is 50Mhz, then bot Q and 2X_Q is way beyond the 35/70Mhz or 40/80Mhz, right?

I hope someone else will try this mod and take it even further.

I'll be attempting it at some point. Hopefully soon! Thanks again for all the great info!

[gborgns]

Da9000,

Q8 ) When you say faster memory, do you mean < 70ns? Or did 70ns work well?

A8)  I used 60ns EDO RAM.  I didn't try slower memory.

Q9) Does the above imply that the 040 on a Mac was alternating between the doubled clock and the non-doubled clock as per bus utilization? In other words, a cure/primitive "power saving" mode based on crude "frequency scaling" ?

A9)   I didn't fully analyze the Quaddoubler PAL.  When I found that it did not work in it's stock form in the NeXT, I started to look at what signals it was monitoring.  The Bus request, Bus Grant and Bus Busy signals stood out.  The Bus Busy line is pulled up and is inactive on the NeXT.  The doubler was somehow using the Bus Busy line on a MAC to know when it could clock the 040 at a higher rate.  That was the extent on my analysis.    So your alternating clock idea was probably close to the best explanation.  

Q10) How were these able to provide a 100Mhz clock? If the input frequency is 50Mhz, then bot Q and 2X_Q is way beyond the 35/70Mhz or 40/80Mhz, right?

A10)  The 80MHz MC88916 on the homemade clock doubler, doubles the 25MHz system clock to 50MHz.  That 50MHz clock is then feed into the 100MHz MC88915 to create the synchronized 50/100MHz clocks for the overclocked 040.  The 100MHz MC88915 is on the system board and replaced the stock 80MHz part.  The 50MHz clock is also fed into the rest of the NeXT circuitry (CLKBCLK) to keep everything synchronized.

Hope that answers your questions.

[da9000]

A8 )  I used 60ns EDO RAM.  I didn't try slower memory.

OK, the reason I asked is because, if I'm not mistaken, the chipset will autoconfigure the necessary timings depending on RAM speeds (70ns, 80ns and 100ns). I guess for 60ns it just uses the 70ns timings.

A9)   I didn't fully analyze the Quaddoubler PAL.  When I found that it did not work in it's stock form in the NeXT, I started to look at what signals it was monitoring.  The Bus request, Bus Grant and Bus Busy signals stood out.  The Bus Busy line is pulled up and is inactive on the NeXT.  The doubler was somehow using the Bus Busy line on a MAC to know when it could clock the 040 at a higher rate.  That was the extent on my analysis.    

Wow, that's pretty good detective work! Mine was just an assumption based on what you said.

A10)  The 80MHz MC88916 on the homemade clock doubler, doubles the 25MHz system clock to 50MHz.  That 50MHz clock is then feed into the 100MHz MC88915 to create the synchronized 50/100MHz clocks for the overclocked 040.  The 100MHz MC88915 is on the system board and replaced the stock 80MHz part.  The 50MHz clock is also fed into the rest of the NeXT circuitry (CLKBCLK) to keep everything synchronized.

Woa, so you're saying that you've "piggy backed" two MC8891x parts? I totally missed that part of the hack. I'm going to look back at the photos again.

When you say "The 100MHz MC88915 is on the system board", you mean the newly replaced U45, near the lithium battery, right?

So basically, you keep the 25Mhz clock (for whatever circuits might be using that), which originates from the PLL IC and not the 100Mhz crystal in the video section, then double that, and use it as the Bus Clock, and then double that to get 100Mhz, which together with the 50Mhz is fed into the CPU. Correct?

Thanks for explaining that. Now I understand it better, because I was confused as to why you also had the MC88916 part and the lack of a 4x line on these parts...

[gborgns]

da9000,

I'll have to power up my system again to see, but I am pretty sure the memory actual showed up as 60ns on boot.

I didn't so much as piggy-back the doublers, as ran them in series to get from 25MHz to 50MHz, then 50MHz to 100Mhz.

U45, the MC88915, is right next to the processor and is under the floppy drive on the slab.  The clock chip next to the lithium battery is the real time clock.

So basically, you keep the 25Mhz clock (for whatever circuits might be using that), which originates from the PLL IC and not the 100Mhz crystal in the video section, then double that, and use it as the Bus Clock, and then double that to get 100Mhz, which together with the 50Mhz is fed into the CPU. Correct?

Correct, except that the 25MHz originates from the TMC chip which uses the 100MHz buffered video clock (CLK100MTTLN) as an input to derive the 25MHz clock.  See the Cslab schematics for more info.

[da9000]

I'll have to power up my system again to see, but I am pretty sure the memory actual showed up as 60ns on boot.

Cool, thanks. Could you also check the speed of the memory you used?

I didn't so much as piggy-back the doublers, as ran them in series to get from 25MHz to 50MHz, then 50MHz to 100Mhz.

U45, the MC88915, is right next to the processor and is under the floppy drive on the slab.  The clock chip next to the lithium battery is the real time clock.

In series, that's what I meant. As for the chips/locations, I mixed it up coz I didn't have the machine infront. Sorry about that.

Correct, except that the 25MHz originates from the TMC chip which uses the 100MHz buffered video clock (CLK100MTTLN) as an input to derive the 25MHz clock.  See the Cslab schematics for more info.

OK, I'll be checking the schematics, so I can fully understand everything before I attempt any hackery.

[da9000]

Do any schematics exist for the non-Turbo models? I can't find any...

[gborgns]

da9000,

The memory is 60ns EDO.  It does come up and display as 60ns memory during verbose boot.

I haven't seen any schematics for the non-turbo models.  The channelu site has been promising them for a while, but I haven't seen anything yet.

[Slab]

I was curious if the CPU is detected as 50Mhz at boot time.  Also, have you run any benchmarks to see how your NeXT compares to the Nitro and Pyro?

[gborgns]

No, the NeXT Rom Monitor shows 33MHz at boot.  The actual CPU frequency is not calculated by the machine, it is hardwired by a set of jumpers which is read on boot.

I have not ran benchmarks vs. the Nitro or Pyro, since I have neither (hence the reverse engineering and work that went into this effort).  I did run benchmarks against the stock 33MHz Turbo Color NeXTStation.

Here are the before and after NeXTWORLD Benchmarks results.

33 MHz:
35046 Dhyrstones/sec
22.251 MIPS
Graphics V/V 12.921 D/V 13.235
Ethernet 25.53 KB/sec*
Disk 2650 KB/sec
Webster 52.518 sec
Compile 12.156 sec

50 MHz:
52631 Dhyrstones/sec
33.417 MIPS
Graphics V/V 8.719 D/V 8.875
Ethernet 27.80 KB/sec*
Disk 3149 KB/sec
Webster 36.968 sec
Compile 9.577 sec

*Average of several tests

Here are the before and after NeXTSTEP Benchmark Suite results.

33 MHz:
Dhrysone 2.1 - 35252 Dhyrstones/sec
22.382 VAX MIPS
NXFactor 2.0 - 0.639

50 MHz:
Dhrysone 2.1 - 53191 Dhyrstones/sec
33.772 VAX MIPS
NXFactor 2.0 - 0.975

I would expect a CPU module that has built in cache memory to have better CPU performance.  However, the 50MHz modification accelerates the entire system, not just the CPU, so the overall performance of the system is enhanced.